1. Field of the Invention
The present invention relates generally to sensing operating conditions of a device, and more particularly, to controlling one or more device parameters based on the sensed operating conditions.
2. Description of Related Art
In certain devices, it may be desirable to adjust device parameters to achieve desired operation of the device. Often, this adjustment, or control, of the device parameters must be performed in an accurate manner to ensure optimal operation of the device. One example of such accurate control may be in the timing of read and write operations in memory devices.
Double data rate dynamic random access memory (DDR DRAM), for example, typically transfers data based on signals on a bi-directional strobe line. DDR DRAM devices typically work in conjunction with a memory controller. The memory controller may generate fixed delays on the “input” strobe signal from the DDR DRAM in order to read data, and may generate fixed delays on the “output” strobe signal so that the DDR DRAM may capture write data from the controller. It may be desirable for the memory controller to generate different fixed delays (i.e., “asymmetric” delays) for the input strobe signal and the output strobe signal.
One way to generate a fixed delay within a memory controller-type application-specific integrated circuit (ASIC) is to chain a string of logic devices (e.g., buffers or inverters) to create a delay line that may be tapped at various locations along the delay line. The actual delay(s) for a given delay line design may vary, however, due to manufacturing process variations, voltage variations within the ASIC chip, and/or temperature variations within the ASIC chip. Moreover, a change in the selection of a tap along the delay line at an inopportune time may cause a glitch on the bi-directional or internal strobe line. Such a glitch may cause the DDR DRAM or memory controller to capture erroneous data, or it may cause the DDR DRAM or memory controller to enter an erroneous state.
Therefore, there exists a need to generate accurate delays in memory controllers.